pcb

1 files changed, 353 insertions, 0 deletions

diff --git a/pcb_boven/openmv/openmv-boards-master/openmv5/onsemi/lbr/AR0234CSSC00SUKA0.lbr b/pcb_boven/openmv/openmv-boards-master/openmv5/onsemi/lbr/AR0234CSSC00SUKA0.lbr
new file mode 100644
index 0000000..2a5b2dc
--- /dev/null
+++ b/pcb_boven/openmv/openmv-boards-master/openmv5/onsemi/lbr/AR0234CSSC00SUKA0.lbr
@@ -0,0 +1,353 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!DOCTYPE eagle SYSTEM "eagle.dtd">
+<eagle version="9.6.2">
+<drawing>
+<settings>
+<setting alwaysvectorfont="no"/>
+<setting verticaltext="up"/>
+</settings>
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+<pin name="DGND3" x="25.4" y="-60.96" length="middle" rot="R180"/>
+<pin name="DGND4" x="25.4" y="-63.5" length="middle" rot="R180"/>
+<pin name="DGND5" x="25.4" y="-66.04" length="middle" rot="R180"/>
+<pin name="DGND6" x="25.4" y="-68.58" length="middle" rot="R180"/>
+<pin name="DGND7" x="25.4" y="-71.12" length="middle" rot="R180"/>
+<pin name="DGND8" x="25.4" y="-73.66" length="middle" rot="R180"/>
+<pin name="DGND9" x="25.4" y="-76.2" length="middle" rot="R180"/>
+<pin name="DGND10" x="25.4" y="-78.74" length="middle" rot="R180"/>
+<pin name="DGND11" x="25.4" y="-81.28" length="middle" rot="R180"/>
+<pin name="DGND12" x="25.4" y="-83.82" length="middle" rot="R180"/>
+<pin name="GNDIO_PHY0" x="-25.4" y="-58.42" length="middle"/>
+<pin name="GNDIO_PHY1" x="-25.4" y="-60.96" length="middle"/>
+<pin name="VAA_PIX1" x="25.4" y="-20.32" length="middle" rot="R180"/>
+<pin name="VAA_PIX2" x="25.4" y="-22.86" length="middle" rot="R180"/>
+<pin name="VAA_PIX3" x="25.4" y="-25.4" length="middle" rot="R180"/>
+<pin name="TEST" x="-25.4" y="-71.12" length="middle"/>
+<pin name="RSVD" x="-25.4" y="-76.2" length="middle"/>
+</symbol>
+</symbols>
+<devicesets>
+<deviceset name="AR0234CSSC00SUKA0" prefix="IC">
+<gates>
+<gate name="G$1" symbol="AR0234CSSC00SUKA0" x="0" y="0"/>
+</gates>
+<devices>
+<device name="" package="AR0234CSSC00SUKA0">
+<connects>
+<connect gate="G$1" pin="AGND0" pad="P$8"/>
+<connect gate="G$1" pin="AGND1" pad="P$26"/>
+<connect gate="G$1" pin="AGND2" pad="P$74"/>
+<connect gate="G$1" pin="AGND3" pad="P$77"/>
+<connect gate="G$1" pin="CAP_1UF_PHY" pad="P$71"/>
+<connect gate="G$1" pin="CLK_N" pad="P$47"/>
+<connect gate="G$1" pin="CLK_P" pad="P$46"/>
+<connect gate="G$1" pin="DATA0_N" pad="P$33"/>
+<connect gate="G$1" pin="DATA0_P" pad="P$32"/>
+<connect gate="G$1" pin="DATA1_N" pad="P$34"/>
+<connect gate="G$1" pin="DATA1_P" pad="P$35"/>
+<connect gate="G$1" pin="DATA2_N" pad="P$57"/>
+<connect gate="G$1" pin="DATA2_P" pad="P$56"/>
+<connect gate="G$1" pin="DATA3_N" pad="P$59"/>
+<connect gate="G$1" pin="DATA3_P" pad="P$58"/>
+<connect gate="G$1" pin="DGND0" pad="P$1"/>
+<connect gate="G$1" pin="DGND1" pad="P$2"/>
+<connect gate="G$1" pin="DGND10" pad="P$61"/>
+<connect gate="G$1" pin="DGND11" pad="P$68"/>
+<connect gate="G$1" pin="DGND12" pad="P$81"/>
+<connect gate="G$1" pin="DGND2" pad="P$5"/>
+<connect gate="G$1" pin="DGND3" pad="P$13"/>
+<connect gate="G$1" pin="DGND4" pad="P$24"/>
+<connect gate="G$1" pin="DGND5" pad="P$28"/>
+<connect gate="G$1" pin="DGND6" pad="P$43"/>
+<connect gate="G$1" pin="DGND7" pad="P$44"/>
+<connect gate="G$1" pin="DGND8" pad="P$49"/>
+<connect gate="G$1" pin="DGND9" pad="P$55"/>
+<connect gate="G$1" pin="DOUT0" pad="P$62"/>
+<connect gate="G$1" pin="DOUT1" pad="P$75"/>
+<connect gate="G$1" pin="DOUT2" pad="P$76"/>
+<connect gate="G$1" pin="DOUT3" pad="P$50"/>
+<connect gate="G$1" pin="DOUT4" pad="P$36"/>
+<connect gate="G$1" pin="DOUT5" pad="P$37"/>
+<connect gate="G$1" pin="DOUT6" pad="P$14"/>
+<connect gate="G$1" pin="DOUT7" pad="P$51"/>
+<connect gate="G$1" pin="DOUT8" pad="P$39"/>
+<connect gate="G$1" pin="DOUT9" pad="P$27"/>
+<connect gate="G$1" pin="EXTCLK" pad="P$82"/>
+<connect gate="G$1" pin="FLASH" pad="P$52"/>
+<connect gate="G$1" pin="FRAME_VALID" pad="P$18"/>
+<connect gate="G$1" pin="GNDIO_PHY0" pad="P$23"/>
+<connect gate="G$1" pin="GNDIO_PHY1" pad="P$54"/>
+<connect gate="G$1" pin="LINE_VALID" pad="P$30"/>
+<connect gate="G$1" pin="OE_N" pad="P$17"/>
+<connect gate="G$1" pin="PIXCLK" pad="P$29"/>
+<connect gate="G$1" pin="RESERVED0" pad="P$10"/>
+<connect gate="G$1" pin="RESERVED1" pad="P$20"/>
+<connect gate="G$1" pin="RESET_N" pad="P$66"/>
+<connect gate="G$1" pin="RSVD" pad="P$69"/>
+<connect gate="G$1" pin="SADDR" pad="P$4"/>
+<connect gate="G$1" pin="SCLK" pad="P$65"/>
+<connect gate="G$1" pin="SDATA" pad="P$53"/>
+<connect gate="G$1" pin="SHUTTER" pad="P$63"/>
+<connect gate="G$1" pin="TEST" pad="P$64"/>
+<connect gate="G$1" pin="TRIGGER" pad="P$40"/>
+<connect gate="G$1" pin="VAA0" pad="P$9"/>
+<connect gate="G$1" pin="VAA1" pad="P$12"/>
+<connect gate="G$1" pin="VAA2" pad="P$73"/>
+<connect gate="G$1" pin="VAA3" pad="P$78"/>
+<connect gate="G$1" pin="VAA_PHY" pad="P$67"/>
+<connect gate="G$1" pin="VAA_PIX0" pad="P$19"/>
+<connect gate="G$1" pin="VAA_PIX1" pad="P$25"/>
+<connect gate="G$1" pin="VAA_PIX2" pad="P$72"/>
+<connect gate="G$1" pin="VAA_PIX3" pad="P$80"/>
+<connect gate="G$1" pin="VDD0" pad="P$3"/>
+<connect gate="G$1" pin="VDD1" pad="P$7"/>
+<connect gate="G$1" pin="VDD2" pad="P$11"/>
+<connect gate="G$1" pin="VDD3" pad="P$21"/>
+<connect gate="G$1" pin="VDD4" pad="P$42"/>
+<connect gate="G$1" pin="VDD5" pad="P$48"/>
+<connect gate="G$1" pin="VDD6" pad="P$79"/>
+<connect gate="G$1" pin="VDDIO0" pad="P$6"/>
+<connect gate="G$1" pin="VDDIO1" pad="P$15"/>
+<connect gate="G$1" pin="VDDIO2" pad="P$16"/>
+<connect gate="G$1" pin="VDDIO3" pad="P$22"/>
+<connect gate="G$1" pin="VDDIO4" pad="P$38"/>
+<connect gate="G$1" pin="VDDIO5" pad="P$41"/>
+<connect gate="G$1" pin="VDDIO6" pad="P$60"/>
+<connect gate="G$1" pin="VDDIO7" pad="P$83"/>
+<connect gate="G$1" pin="VDDIO_PHY" pad="P$45"/>
+<connect gate="G$1" pin="VDD_DATA" pad="P$70"/>
+<connect gate="G$1" pin="VDD_PHY" pad="P$31"/>
+</connects>
+<technologies>
+<technology name=""/>
+</technologies>
+</device>
+</devices>
+</deviceset>
+</devicesets>
+</library>
+</drawing>
+</eagle>