From 74a67a1841d8ee094637b5dcc9704847484b1b0a Mon Sep 17 00:00:00 2001
From: abel <71026016+ableTI@users.noreply.github.com>
Date: Fri, 3 May 2024 12:41:34 +0200
Subject: Add files via upload

---
 .../CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG       | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 pcb/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG

(limited to 'pcb/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG')

diff --git a/pcb/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG b/pcb/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG
new file mode 100644
index 0000000..fb91cad
--- /dev/null
+++ b/pcb/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/EDI2CAP.CFG
@@ -0,0 +1,35 @@
+;>------- Configuration parameters: -------<
+;>------Check EDIF2CAP.PDF for details ----<
+
+[OrCAD Writer]
+
+SuppressWarnings = 0	
+ConvertOnlyLibs = 0
+UnitMeasurement = default
+PinToPin = 0
+Grid = 0
+EnableOffgridObjects = 0
+GenerateIniFile = 1
+OrcadConventions = 1
+UseDesignatorsForPackaging = 1
+DesignatorsEndOnLetters = 0
+DesignatorsSameInHierarchy = 1
+GeneratePinNumbers = 0
+GeneratePortSymbols = 1
+GenerateOffPageConnectors = 0
+GenerationVisible = 1
+CaptureLibsWithUserPackages = ""
+SystemNetNamePrefix = ""
+BackgroundTextScale = 0.8
+DefaultNetNameScale = 0.3
+StandardPageSize = 0
+EliminatePageText = 0
+SmashTitleBlock = 0
+PinDisplayStyle = orcad
+TopView = ""
+ComponentsMode = 0
+ReplacePartWithNoPinsWithTitleBlock = 0
+ChangeBusBaseThatEndsOnDigit = 0
+ProcessBackAnnotation = 1
+
+[Mapper]
-- 
cgit v1.2.3