From 5a9a984cc18f8403cc7f50c37fa3cc96f64b75ff Mon Sep 17 00:00:00 2001 From: Abel Tim Date: Sat, 4 May 2024 11:21:20 +0200 Subject: Commit message --- .../CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 pcb_onder/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr (limited to 'pcb_onder/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr') diff --git a/pcb_onder/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr b/pcb_onder/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr new file mode 100644 index 0000000..3891e12 --- /dev/null +++ b/pcb_onder/cc6/LIB_CC6-1203SR-E/CC6-1203SR-E/OrCAD_Allegro16/padstack1.scr @@ -0,0 +1,20 @@ +setwindow Form.padedit +######################## New PadStack ######################### +pse_new +fillin "r320_120.pad" +FORM padedit units Millimeter +FORM padedit layers + +FORM padedit grid row 1 +FORM padedit geometry Rectangle +FORM padedit width 1.200 +FORM padedit height 3.200 +FORM padedit x_offset 0 +FORM padedit y_offset 0 +FORM padedit geometry_th Null +FORM padedit geometry_ant Null + +FORM padedit single YES +FORM padedit plating Non-Plated +pse_save_as +fillin "r320_120.Pad" -- cgit v1.2.3